Development of an advanced 32-bit airborne computer

An advanced 32-bit airborne computer was developed to fulfil the needs of the ICAAS (Integrated Control and Avionics for Air Superiority) program, with applicability to other programs with similar requirements. The computer may contain up to four processors that are based on the MIPS R-3000 reduced-instruction-set microprocessor. This four-processor configuration is capable of approximately 20 million instructions per second throughput (based on VAX 11/780) and 32-bit words of memory. Memory is configurable in blocks of nonvolatile electrically reprogrammable devices for program storage and RAM for read/write scratchpad. The R-3000 has been selected by the Joint Integrated Avionics Working Group as one of two standard 32-bit architectures. A high-speed parallel system bus is used internally, for interprocessor communications, whereas two 1553 multiplex bus interfaces are used for external communications. An operating system is also in development, providing the application programmer a fully compliant Ada environment that allows the downloading and debugging of software and realtime execution without concern for hardware peculiarities. The development of this computer, the tradeoffs that were considered, and the final architecture and features that evolved are described. >