EOS/ESD protection circuit design for deep submicron SOI technology

Deep submicron silicon-on-insulator (SOI) is potentially an important technology for low voltage applications because of advantages in processing, speed, subthreshold conduction and latchup immunity. However, little attention has been given to EOS/ESD protection circuit design issues for submicron SOI technology. Multi-finger grounded gate NMOS (GGNMOS) devices have been used as effective output protection devices for bulk Si technology. In this paper, we investigate the failure modes of GGNMOS devices designed for a 0.3 /spl mu/m fully depleted SOI technology. We provide a theoretical comparison between the EOS/ESD performance of bulk and SOI technologies. We also provide practical design guidelines for effective protection circuit design in SOI technology.