In-design DFM CMP flow for block level simulation using 32nm CMP model

Traditionally model based CMP check and hotspot detection are only done at the top level of the design because full chip assembly is required to capture CMP long range effect. When manufacturing hotspots are found just before tape out and layout modification is required, this can disrupt the overall schedule by repeating the verification steps with the changed layout. Hence getting feedback at early design stage is critical to ensure that the design is correct by construction. In this paper, we present a model-based CMP-DFM methodology which is used at early design phases to avoid CMP related manufacturing failures. An accurate CMP model has been developed and used to predict surface topographies for 32nm designs as well as physical hotspots caused by dishing, erosion, and depth of focus. We demonstrate how to apply a characterized 32nm CMP physical model to run block level simulation with little or no context information. The block level simulation methodology allows designers to check block robustness against any possible surrounding environments in which the block may be placed. This approach can be taken for corner case analysis in CMP-aware RC extraction.