Vertically-stacked strain Si/SiGe heterojunction CMOS device structure and preparation method thereof

The invention discloses a vertically-stacked strain Si/SiGe heterojunction CMOS device structure and a preparation method thereof. The device comprises a silicon substrate, a relaxation SiGe buffer layer, a relaxation Si0.7Ge0.3 virtual substrate, an n delta doping layer, a relaxation Si0.7Ge0.3 interval layer, a strain Si trench, a relaxation Si0.7Ge0.3 intermediate layer, a strain Si0.5Ge0.5 trench, a relaxation Si0.7Ge0.3 cap layer and a Si cap layer from the bottom up in sequence. An n-MOSFET trench adopts a tensile strain Si material, a p-MOSFET trench adopts a compression strain SiGe material, and the n-MOSFET and the p-MOSFET adopt a vertically-stacked structure, and share one polycrystalline SiGe gate electrode, so that electron and hole migration rates are improved greatly, speed and integration level of chips are improved, and new technological approaches are provided for high speed and high frequency development of the Si device and an integrated circuit.