Design and performance of an analog delay and buffer chip for use with silicon strip detectors at LHC

Abstract An analog delay and buffer chip has been designed and built in 1.2 μm CMOS technology to be used in silicon detectors at LHC. Measurements on the performance of the prototype chip are presented. The storage cells variations are smaller than 0.65 rms mV, i.e. 1 100 of the signal in its input for a minimum ionizing particle.