Fan-out Wafer Level Packaging of GaN Components for RF Applications

Driven by 5G or radar applications there is an increasing market for GaN device for RF power applications. GaN component packaging is done today mainly by wire bonding in combination with expensive ceramic based packaging solutions. Cost efficient Fan-out Wafer Level Packaging (FOWLP) is considered a promising solution for GaN devices offering short and low inductance interconnects, high miniaturization, good thermal solutions, potential lower cost and the possibility of integrating passive components and structure in the package and redistribution layer.However, GaN packaging also bears some challenges which have to be considered when developing new packaging technologies. GaN devices are typically quite thin in the range of 100 μm and have fragile air bridge structure on the active die side. Both aspects have to be taken into account for FOWLP concerning pick-and-place assembly, compression molding and debonding from thermal release tape. Also the influence of the redistribution layer (RDL) on the air bridges and RF performance have to be analyzed. Au is used as pad and component backside metallization. Here a good adhesion must be guaranteed to the interface materials involved. Access to the backside metallization of the GaN device is required for thermal dissipation and electrical connection if needed. The thermal concept is an important factor as the junction temperature should not exceed certain values. Besides the limits of the component itself the polymers involved as the dielectric material and the epoxy molding compound will degrade under long-term high temperature load and thus will cause reliability issues. In contrast to Si dies, the backside of the GaN device cannot be accessed by backgrinding because the metallization must not be damaged or removed. Here new solutions for backside connections during FOWLP packaging and compression molding are required.The paper will describe the technology development of a GaN based power amplifier in Fan-out Wafer Level Packaging technology. For the GaN backside access two different approaches have been evaluated, first the attachment of a Cu heatsink on the GaN backside before molding followed by a backgrinding step into the Cu heatsink and second the drilling of vias through the mold to the GaN backside followed by direct metallization of the vias for thermal and possible electrical connection. The thermal release tape used has been carefully selected and the process steps pickand-place assembly, compression molding and debonding have been optimized to avoid any damage of GaN die and air bridges. Influences of the packaging materials on the RF performance of the die have also been tested. Finally the different technology blocks developed have been combined to build a GaN based power amplifier in FOWLP.