An adaptive parallel system dedicated to projective image matching

This paper proposes an adaptive and scalable system prototype for projective image matching. This prototype PC board includes a new parallel systolic VLSI-/spl mu/PD (implemented in an FPGA (Xilinx Virtex circuit, XCV300), a DSP and a microcontroller only. The /spl mu/PD circuit is a VLSI dedicated to real-time image line/column matching, which uses the modified dynamic programming algorithm. Its internal architecture is adaptive, in function of more or less hard final application temporal constraints. The architecture adaptativity, scalability and software virtualisation of the /spl mu/PD circuit permit one to match images of any size. The processing speed (2000 faster than image matching sequential solution), system volume and system cost have been optimised according to A/sup 3/C circuit/system design methodology (A/sup 3/C-algorithm-architecture adequation under constraints).