FLIP CHIP CONNECTIONS USING BUMPS, WELLS, AND IMPRINTING

A conceptual framework for a new type of flip chip attachment is proposed. Gold stud bumps are provided on the chips, and wells filled with solder paste are provided on the board. Pushing the stud bumps into the wells provides a bump/well connection, and heat is applied to melt the solder and make a permanent connection. An area array of bump/well connections can have a pitch of 100 or less. The connections are projected to be mechanically strong, to support operating frequencies of 10GHz and above, and to support replacement of defective chips as many times as necessary. Imprinting provides a fabrication method having sufficient precision to shrink the trace and dielectric feature sizes by a factor of around 20 compared with conventional FR-4 boards, while maintaining 50 trace impedance. The imprinting method is also well suited to building circuits on copper substrates, which can result in substantial cooling advantages. The precision of imprinting is also used to eliminate redistribution layers that are normally required between the fine pad pitch of IC chips and the coarser pad pitch of a conventional board. By also fabricating the wells using a variation of the same imprinting process a low assembly cost is achievable, potentially below 0.06 cents per lead. This compares with an industry cost as high as 2.5 cents per lead for performance flip chip PBGA 1 . The most advanced materials can be used for the interconnection circuits including copper conductors and Cytop 2 as the dielectric. At 10 GHz, Cytop has a dielectric constant of 2.1 and a dissipation factor of 0.0007. The proposed manufacturing methods and assembly techniques can be applied to a broad range of microelectronic systems including high performance circuit boards, high density cables and connectors with controlled impedance traces, integrated passives, RF circuits, and stacked die packages.