Method of reducing thermal load in 3D NAND flash memory

The invention provides a method of reducing thermal load in 3D NAND flash memory, comprising the steps of deposing a substrate stacking structure and etching the substrate stacking structure to form achannel and a silicon groove at the surface of the substrate; conducting post etch treatment (PET) on the channel and the silicon groove; adopting DHF for a first low temperature cleaning to remove oxide at the silicon groove interface; adopting NH4OH for second cleaning to remove amorphous silicon at the silicon groove interface. The invention is advantageous in that the thermal load of the device can be reduced, which is favorable for performance at the peripheral period and is capable of improving the morphology at the bottom of SEG; the improvement of the morphology at the bottom of SEG can improve the homogeneity of the growth height of silicon epitaxy, and further improve the integral performance of the 3D NAND flash memory.