A high performance hardware architecture for the H.264/AVC half-pixel motion estimation refinement

This work presents a high performance hardware architecture for the H.264/AVC Half-Pixel Motion Estimation Refinement. This design can process very high definition videos like QHDTV (3840x2048) in real time processing (30 frames per second). It also presents a very optimized arrangement of interpolated samples, which is the main key to achieve an efficient search. The architecture was fully described in VHDL, synthesized to two different Xilinx FPGA devices and achieved the best results when compared to related works.