Deep n-well MAPS in a 130-nm CMOS technology: Beam test results

Abstract We report on recent beam test results for the APSEL4D chip, a new deep n-well MAPS prototype with a full in-pixel signal processing chain obtained by exploiting the triple well option of the CMOS 0.13 μ m process. The APSEL4D chip consists of a 4096 pixel matrix (32 rows and 128 columns) with 50 × 50 μ m 2 pixel cell area, with custom readout architecture capable of performing data sparsification at pixel level. APSEL4D has been characterized in terms of charge collection efficiency and intrinsic spatial resolution under different conditions of discriminator threshold settings using a 12 GeV/ c proton beam in the T9 area of the CERN PS. We observe a maximum hit efficiency of 92% and we estimate an intrinsic resolution of about 14 μ m . The data driven approach of the tracking detector readout chips has been successfully used to demonstrate the possibility to build a Level 1 trigger system based on associative memories. The analysis of the beam test data is critically reviewed along with the characterization of the device under test.