Bit-swapping linear feedback shift register (LFSR) for power reduction using pre-charged XOR with multiplexer technique in built in self-test

Testing becomes an inevitable part of the VLSI circuit. All the circuits or products must be verified before delivery. The data collected during testing is used to remove the faulty parts from the products and help to enhance the design and manufacturing process and improve the returns as well. There are several contributions made by researchers which are majorly based on Linear Feedback Shift Register (LFSR), bit swapping LFSR and dual threshold bit swapping LFSR methods. Reduction of delay, power consumptions and fault coverage are considered as major factors from the above methods. The proposed approach uses Bit Swapping-Linear Feedback Shift Register (BS-LFSR) architecture which integrates pre-charge, set-reset and gate replacement with mux techniques have alleviated the inherent drawbacks of linear feedback shift register and produced better results. Pre-charge method is reducing the delay and power consumption there by maximizing the operating frequency angle with high performance. High fault coverage is achieved through set and reset technique. Multiplexers mainly employed to minimize the delay and power consumption. BS-LFSR pattern generators are used to decrease the transition power from high switching action. These are producing an arbitrary test sequences with less power of switching by determining the pretense space between two subsequent designs. The area is reduced with the help of combinational logic. Experimental evaluation is done using ISCAS89 benchmark datasets. From the results, it is inferred that the fault coverage is increased and power consumptions are reduced.