SEMI-RECURSIVE VLSI ARCHITECTURE FOR TWO DIMENSIONAL DISCRETE

This paper presents an efficient two-dimensional discrete wavelet transform (2-D DWT) VLSI architecture which calculates the 2D DWT for image processing in real-time. The proposed architecture, Semi-recursive 2-0 DWT VLSI architecture, has the minimum WW cost of internal word length, data-bus utilization, scheduling control overhead and storage size. Compared with the conventional recursive 2-D DWT VLSI architecture, the size of multipliers and registers are reduced by the amount of 13% and 34%. Furthermore, the Semi-recursive 2-D DWT VLSI architecture exploits the lapped block processing and hence has the minimum transposition storage size and the short latency.