BKVex: An Adaptable VLIW Processor and Design Framework for Reconfigurable Computing Platforms

Reconfigurable computing has been considering as one of the main approaches to utilize billions transistors integrated in a chip in this nanoscale era. In this paper, we introduce our adaptable VLIW processor whose organization is reconfigurable at design time so that the processor is optimized for a particular program or application-domain. Issue-width, the number of registers, instruction and data caches, and functional units availability are reconfigurable parameters. The processor, in all configurations, can function in a 5-stage pipeline model to improve performance. Moreover, we present our design framework that helps users determine an optimized VLIW processor configuration according to requirements of the executed program. The design framework also allows users to implement the VLIW processor on an FPGA-based platform without knowing HDLs. We synthesize the processor in different configurations with four FPGA technologies. The synthesis results show that our processor can work at up to 174.89MHz with the Xilinx Virtex 7 technology. When compared to NIOS II RISC-like softcore processor at the same working frequency, our adaptable VLIW processor achieves speed-ups by up to 22.6x.