On the use of the thermal step method as a tool for characterizing thin layers and structures for micro and nano-electronics

This work concerns the use of the thermal step method (TSM) for measuring electric charge in metal-oxyde-semiconductor (MOS) structures used in micro and nano-electronics. The TSM is a non destructive method for quantifying and localizing the electric charge in solid insulating materials and structures. Its principle is the application of a low thermal step to a short-circuited or dc-biased sample and the analysis of a current response, which depends on the charge present in the device. An adaptation of the technique (so far used in thick insulating materials and structures for electrical engineering) to short-circuited and biased MOS devices, is described. Results obtained on biased MOS structures and their correlation with classical capacitance-voltage (C-V) measurements are given. Estimations, by the TSM, of the amount of charge trapped in the oxide and of the space charge penetration depth in the silicon substrate are presented.