Old Web
English
Sign In
Acemap
>
Paper
>
Design of a 3.3-V 1-GHz CMOS Phase Locked Loop with a Two-Stage Self-Feedback Ring Oscillator
Design of a 3.3-V 1-GHz CMOS Phase Locked Loop with a Two-Stage Self-Feedback Ring Oscillator
2000
Moon Yeon Kug
Yoon Kwang Sub
Han Chang-Ho
Keywords:
Delay line oscillator
Nuclear magnetic resonance
Physics
RC oscillator
Voltage-controlled oscillator
Electronic engineering
Digitally controlled oscillator
Phase-locked loop
Delay-locked loop
Vackář oscillator
Variable-frequency oscillator
Condensed matter physics
Optoelectronics
Correction
Source
Cite
Save
Machine Reading By IdeaReader
1
References
2
Citations
NaN
KQI
[]