A low power and low in-band phase noise W-band frequency synthesizer in 65 nm CMOS

A fully integrated 79 to 87 GHz frequency synthesizer is proposed, which combines a W-band push–push ×4 frequency multiplier and a K-band divider-less phase locked loop (PLL) with sampling phase detector. The circuit is verified in a standard 65 nm CMOS process. The frequency synthesizer consumes 54 mW totally, and the measured phase noise of divide-by-2 frequency is −100.1 and −106.2 dBc/Hz at 100 kHz and 1 MHz offset, respectively. © 2014 Wiley Periodicals, Inc. Microwave Opt Technol Lett 56:2014–2018, 2014