An experimental 5 ns BiCMOS SRAM with a high-speed architecture

A RAM which uses circuit techniques and architectural innovation to achieve the performance demanded by today's systems is described. An input buffer/level translator, a current sense amplifier, and a high-speed architecture are used in this RAM to achieve the 5-ns access time along with the 0.6-mm BiCMOS technology. The chip is organized as 128 K-wordst8-b wide using a 4T2R memory cell of 28 mm 2