Models and Analysis Techniques for Systematic Design and Verification of Frequency Synthesizers

After a brief introduction to the top-down design and bottom-up verification methodology, this chapter has presented the necessary models for the systematic design of a frequency synthesizer used in telecommunication applications. The models are tuned towards the evaluation of the trade-off between the loop settling time and phase noise performance at the output node. Both models for top-down design and bottom-up verification were presented. The validity of these models was illustrated using a 1.8 GHz CMOS frequency synthesizer.