Hardware efficient block matching algorithm based on modified differential evolution optimization for fast motion estimation

Nowadays, the requirement of quality videos can increase due to the growth of video coding applications, but most applications affected by motion estimation. Recently block matching (BM) algorithms performed very effective and simple for implementation than other motion estimations approach. Different BM architectures are used to estimate the motion with real-time speed but not in quality factors. In this paper, we concentrate to enhance both metrics are speed and quality. The hardware design of BM algorithm is implemented using the modified differential evolution optimization (MDEO), which provides the quality requirement without affecting the area, power, and delay. The main objective of our MDEO-BM algorithm is to computes the motion vector as faster manner without compromising quality. Hardware structure of our MDEO-BM algorithm implemented in Verilog language using Virtex-6 FPGA family and synthesized using Xilinx ISE Design Suite 14.5. The proposed architecture of MDEO-BM algorithm achieves a critical path delay of 4.487 ns and the maximum frequency of 222.875 MHz. The performance of proposed architecture is analyzed by delay, area, and power and quality of estimated motion vectors are analyzed by PSNR with different test video sequences. Simulation results shows that our MDEO-BM algorithm performs efficient in terms of hardware utilization, power consumption, maximum clock frequency and quality metrics.