Charge Based Mixed-Signal Multiply-Accumulate Circuit for Energy Efficient In-Memory Computing

A feasibility study of an energy efficient analog mixed-signal multiply-accumulate circuit with multi-bit resolution is presented. With a derived hardware-specific neuron model a ResNetV2 with 4 bit quantized weights is trained on a CIFAR10 dataset achieving 90% accuracy. The simulated energy efficiency of the multiply-accumulate circuit is 2.840 fJ per multiply-accumulate operation.