Formal verification of high-level data-flow synthesis designs using relational modeling and symbolic computation

This paper presents a formal verification methodology of high-level data-flow synthesis process. Typically, given a data-flow description, the high-level data-flow synthesis tools perform high-level restructuring and data-flow transformations to produce an optimized architectural implementation. How to verify the correctness of the synthesis results is a key issue within the high-level data-flow synthesis process. Our approach adopts the relational modeling techniques from Kleene algebra with tests (KAT) and the symbolic computation methods from polynomial algebra to solve this verification problem. In this paper, we show how to extract target properties from the data-flow description by using KAT and how to construct the polynomial representation for the architectural implementation. Further, we demonstrate how a symbolic computation-based decision procedure is integrated into our framework to perform verification in a generalized bounded model checking (BMC) style. The experimental results on some public benchmark and practical designs demonstrate the efficiency of our approach and its applicability to large data-flow designs.