Process-variation aware design optimization of an integrated microprobe detector

Invasive attacks in integrated systems make use of microprobes to sense information in specific bus lines. Recent techniques for protecting circuits from this kind of attack are based on the detection of deviations in the expected bus line capacitance caused by the attacking probe. The strategy is to convert capacitance deviations into delay deviations, followed by time-to-digital conversion to provide a signature that is used to identify the occurrence of a probe attack. However, the sensitivity to delay deviation in conventional CMOS circuits is highly related to individual sizes of elements that compose the protecting circuit and to manufacturing variations. It opens the opportunity for circuit optimization in order to maximize the performance of time-to-digital conversion. In this paper, a multi-objective optimization-based methodology is proposed to optimize the required silicon area as well as the robustness and parametric manufacturing yield of a microprobe detector. We present the required computational modeling of the circuit objectives and constraints for a successful application of optimization methods. The optimization approach is based on multi-objective particle swarm optimization and on Monte Carlo performance simulation. It explores the design space with regard to the trade-off between silicon area and yield. Results show that this approach can reduce the required circuit gate area up to $$50\%$$ compared to manual sizing, while guaranteeing high manufacturing yield.