A fully adaptive 19-to-56Gb/s PAM-4 wireline transceiver with a configurable ADC in 16nm FinFET

Trends in IoT and cloud computing continue to accelerate bandwidth demand, requiring technology innovation to cover 50G, 100G and 400G ports without significant increase in cost or power per bit. In order to mitigate the cost of infrastructure upgrade, the industry has proposed a standard for 56Gb/s PAM-4 interfaces [1] that can support legacy channels using Forward Error Correction (FEC). Recent publications achieve good pre-FEC BER performance using ADC-based receivers [2,3], but the power consumption (e.g. >550mW per lane at 56Gb/s excluding DSP/digital power in [2]) could be prohibitive for products with large numbers of transceivers. This paper demonstrates a fully integrated and adaptive 19-to-56Gb/s PAM-4 (9.5-to-28Gb/s in NRZ mode) transceiver implemented in 16nm FinFET technology that consumes significantly lower power.