Stuck-at Fault Resilience using Redundant Transistor Logic Gates

The paper demonstrates a novel design for a stuck-at CMOS gate based on dual-purpose redundancy. It combines detection and mitigation against common stuck-at fault conditions to improve fault tolerance without the need to replicate the entire circuit. Using fault rate analysis, the principle is outlined and showed for NAND gate designs. For single fault events, the relationship between fault rate and the number of redundant elements is evaluated in order to identify designs that achieve full fault masking and fault detection coverage with minimum redundancy overhead. The combination of fault masking and detection could be useful for future work on self-reconfiguring platforms.