Timing-Abstract Circuit Design in Transaction-Level Verilog

Given the complexity of modern integrated circuits, design reuse is essential, but current hardware description languages do not adequately address reuse challenges for many classes of design. Processor cores, as an example, are shaped by cycle-level interactions, and leveraging such designs into environments with different timing constraints requires retiming, repipelining, and microarchitectural changes. Making these changes at the register-transfer level requires significant rewriting. Abstraction is needed, but the abstractions of SystemC and OpenCL are more appropriate for loosely-coupled microarchitectural interactions. A timing-abstract modeling approach is presented that separates the concerns of behavior and timing. Timing-abstract behavior is specified within the context of pipelines, and logic within pipelines is assigned to pipeline stages as a matter of implementation detail. Sequential elements are generated by tools from the pipelined specification. Logic can be retimed easily, without the risk of introducing functional bugs, so design and verification effort can be focused on the behavioral changes required to retarget a design to a context with different timing constraints. As a secondary benefit, significantly less source code is required to specify register-transfer-level detail.