Progress in HTS sampler development

Abstract This paper describes an overview of our plan and recent progress on the HTS sampler development with the aim of demonstrating its potential performance of a bandwidth over 100 GHz using a compact cryocooler. Several changes from the NEC’s former work have been made in the device fabrication process, the circuit design and the system design. We employed the HTS circuit process with a lower ground-plane structure, and improved the circuit design and the related packaging technology, which enabled a higher bandwidth. We have focused on observing 50 GHz waveforms by the sampler as the mid-point goal, and then succeeded in observing a 45 GHz sinusoidal waveform in magnetically coupled current measurement and a 50 GHz waveform in voltage measurement with a high-frequency module. An on-chip sampler observing short-duration sampling pulse was also designed and the observation was successfully demonstrated.