An integrated circuit comprising a fin structure

Embodiments of the invention relate generally to a method of manufacturing an integrated circuit, a method of manufacturing a cell array, an integrated circuit, a cell array and a memory module. In one embodiment of the invention, a method is provided for fabricating an integrated circuit having a cell arrangement, the method comprising forming at least one semiconductor fin structure having a region for a plurality of fin field-effect transistors, wherein the area of ​​each fin field-effect transistor a the first region having a first fin structure width, a second region having a second fin structure width, said second fin structure width is smaller than the first fin structure width. Further forming a plurality of charge storage areas at or above the second regions of the semiconductor fin structure.