Considerations for fine hole patterning for the 7nm node

One of the practical candidates to produce 7nm node logic devices is to use the multiple patterning with 193-immersion exposure. For the multiple patterning, it is important to evaluate the relation between the number of mask layer and the minimum pitch systematically to judge the device manufacturability. Although the number of the time of patterning, namely LE(Litho-Etch) ^ x-time, and overlay steps have to be reduced, there are some challenges in miniaturization of hole size below 20nm. Various process fluctuations on contact hole have a direct impact on device performance. According to the technical trend, 12nm diameter hole on 30nm-pitch hole will be needed on 7nm node. Extreme ultraviolet lithography (EUV) and Directed self-assembly (DSA) are attracting considerable attention to obtain small feature size pattern, however, 193-immersion still has the potential to extend optical lithography cost-effectively for sub-7nm node. The objective of this work is to study the process variation challenges and resolution in post-processing for the CD-bias control to meet sub-20nm diameter contact hole. Another pattern modulation is also demonstrated during post-processing step for hole shrink. With the realization that pattern fidelity and pattern placement management will limit scaling long before devices and interconnects fail to perform intrinsically, the talk will also outline how circle edge roughness (CER) and Local-CD uniformity can correct efficiency. On the other hand, 1D Gridded-Design-Rules layout (1D layout) has simple rectangular shapes. Also, we have demonstrated CD-bias modification on short trench pattern to cut grating line for its fabrication.