A 0.012mm 2 , 0.96-mW All-Digital Multiplying Delay-Locked Loop Based Frequency Synthesizer for GPS-L4 band

This paper presents a low-power fully digital multiplying delay-locked loop (MDLL) based frequency synthesizer for GPS-L4 band. In the proposed MDLL, the supply noise sensitivity and RMS jitters are mitigated by implementing the core logic of frequency-operated digital low-dropout regulator (DLDO) in the main loop. The proposed MDLL in a 40 nm CMOS process exhibits an in-band phase noise of -107 dBc/Hz at 100 kHz offset with < 1ps of RMS jitter while consuming maximum power of 0.96 mW at nominal supply voltage of 1.0 V.