Effects of I–V Measurement Parameters on the Hysteresis Effect and Optimization in High-Capacitance PV Module Testing

In high-efficiency crystalline silicon photovoltaic (PV) modules, the internal capacitance may lead to a strong hysteresis effect in current–voltage ( I–V ) measurements. This hysteresis introduces a significant error in measurement results. This work investigates the nature of the hysteresis error ( ϵ ) variation caused by different measurement parameters in the I–V measurement. The effects of the I–V measurement parameters on the hysteresis error of a silicon heterojunction PV module were investigated through some comparative tests. Among all the parameters, the number of sweep points ( N ) and the voltage hold time ( T h ) of each sweep point are the most important factors affecting the value of the hysteresis error in I–V measurements. With the same total T h , the ϵ variation can be expressed as a single-peak curve with the increase of N . With the same T h for each point, ϵ increases in proportion to the reciprocal of N . To explain the origin of the theoretical relation among ϵ , T h , and N , an analytical equation was derived according to the diode model circuit and first-order circuit analysis method. Based on the derived equation, a parameter-setting optimization method for high-capacitance PV module measurements is proposed to precisely control the hysteresis error through certain simple pretests.