Two-Step Flash ADC Using Standard Cell Based Flash ADCs

In this paper, a 9-bit resolution two-step Flash Analog-to-Digital Converter (ADC) is designed using standard cell based comparators. The standard cell-based comparators are designed with basic gates like NOT, NOR, NAND and their combinations in order to generate the required built-in reference voltage. This replaces the need of conventional dynamic comparators and the resistor ladder. The NMOS and PMOS used in the standard cells are designed using a constant aspect ratio to facilitate the semi-automated synthesis. These comparators consume less area, power and are less sensitive to noise. The ADC is designed in a CMOS 180 nm process with supply voltage of 1.8 V. The architecture operates at a 28.57 MS/s with a power consumption of 7.68 mW. The effective number of bits achieved for the design is 8.41 bits.