48nm Pitch cu dual-damascene interconnects using self aligned double patterning scheme

For sub-64nm pitch interconnects build, it is beneficial to use Self Aligned Double Patterning (SADP) scheme for line level patterning. Usually a 2X pitch pattern was printed first, followed by a Sidewall Image Transfer (SIT) technique to create the 1X pitch pattern. A block lithography process is then used to trim this pattern to form the actual designed pattern. In this paper, 48nm and 45nm pitch SADP build will be used as examples to demonstrate the SADP patterning scheme. General discussions about this patterning scheme will be provided including: 1) the process flow of this technique, 2) benefits of the technique vs. pitch split approach, 3) the design impact and limitation, and 4) the extendability to smaller line pitch build.