Design of a Low Temperature Drift Undervoltage Lockout Circuit-Used for GaN FET Power Driver IC

In order to improve the stability of the GaN FET power driven integrated circuit, the integrated circuits usually design corresponding protective circuit modules, such as overcurrent, over temperature, under-voltage protection circuit, etc. In this paper, combined with the characteristics of GaN FET, based on the 0.18 m BiCMOS technique, a novel UVLO circuit used in GaN FET power driven integrated circuits is designed. The average temperature drift of turn on circuit voltage threshold(VDDTH+) is 0.12V, the maximum temperature drift is 0.481V, the average temperature drift of turn off threshold voltage(VDDTH-) is 0.03V, the maximum temperature drift is 0.142V; the VDDTH+ and VDDTH-are 4.241v and 3.885v; The hysteresis voltage is 356mv between VDDTH+ and VDDTH-, improved the circuit anti interference ability. The simulation results show that the circuit can output low voltage logic signals in under-voltage, and has low temperature drift and voltage hysteresis function, which has important significance for improving the performance of GaN FET power drive integrated circuit.