Development of FPGA Based Network on Chip for Circumventing Spam

With the growing popularity of Internet and extensive use of E-mail as a communication media, the volume of Spam mails has seen to be growing at a phenomenal rate. The growing volume of Spam mails as well as their mutating nature annoys people and affects work efficiency significantly. The unsolicited emails or Spam’s used to be deliberated of as just a nuisance, in the past few decades, however in the last few years; their annoyance has reached to epidemic proportions. Thus the Spam mails have has really become a nightmare for every email user. This chapter presents Anti-Spam solution prototyped on Xilinx Spartan 3e FPGA and designed using Handel C. We have adopted the hardware-software co-design methodology and the same is described from scratch. Two IP cores have been designed viz. Content Addressable Memory (CAM) and Bloom Filter in Handel C and the same have been deployed on the Spartan 3e FPGA along with the customizable version of Microblaze. The main contribution is reporting the technical know how related to the co-design aspects that comprehends synergic mixture of soft IP cores of the content addressable memory (CAM) and bloom filter realized both in hardware and software with the Xilinx Microblaze processor. The toolset used for the hardware-software co-design is the Xilinx Embedded Design Kit (EDK). The design flow comprises of the IP core design in Handel-C, embedded in EDK driven by the central customized core of Microblaze.