A Highly-Efficient Crossbar Allocator Architecture for High-Radix Switch

The present contribution explores the allocator design for high-radix switches and implements a highly-efficient allocator PWF(Parallel WaveFront) for achieving high throughput. Based on wavefront allocator, PWF allocator realizes fast allocation within one cycle to avoid timing loop, and it proposes parallelized matching strategy on cyclical priority to supply allocation fairness as well as utilizing greedy policy to reach the maximal match number. Implemented under 32nm CMOS technology, the evaluation results of PWF hardware cost show that the area and power consumption compared to wavefront allocator are slightly increased by 32.8% and 36.8%, and the critical path delay under 8x8x8 switch is less than 0.5ns which satisfies the requirement of GHz-level frequency design for high-radix switch. By further estimating the allocation efficiency, PWF reduces the request schedule time by 61.2% and 65.7%, and increases the immediate request schedule number averagely by 38.9% and 46.7% in comparison with wavefront allocator. Then, the efficiency improvement is also revealed by the distinctly decreased average schedule time and average response time compared with wavefront and DRRM allocators, yielding apparent advantages on improving allocation performance and providing good allocation fairness.