Microelectronic integrated circuit including hexagonal cmos type nand gated device

PROBLEM TO BE SOLVED: To reduce the length of wires of interconnection on an integrated circuit by a method, wherein the microelectronic integrated circuit comprises a microelectronic device, which is formed of closely packed hexagonal arrangements on a semiconductor substrate so as to minimize the use of space of a circuit on the substrate. SOLUTION: A gate device 30 is formed on a substrate 32 and includes a logic ALL element 133 having a hexagonal outer edge 134, which includes first to sixth edges 134-1, 134-2, 134-3, 134-4, 134-5 and 134-6. Moreover, the device 30 comprises an ANY element 233 having a hexagonal outer edge 234, which includes first to sixth edges 234-1, 234-2, 234-3, 234-4, 234-5 and 234-6, and an active region 236. For example, for minimizing the area which is required by the device 30, of a circuit on the substrate 32, the edge 134-4 of the element 133 and the edge 234-6 of the element 233 are closely adhered to each other and are commonly packed closely in a microelectronic device. Thereby, the distance of wirings can be reduced.