A load-pull based device evaluation method for bias modulated applications

In this paper an evaluation method for RF-Power transistors for high-efficiency applications using drain bias-modulation is presented. The method is based on post processing of continuous wave load-pull data under varying power, drain bias and impedance matching. Using this method technology limitation can be investigated and the impact of various modulator models on device performance can be predicted at an early stage in the design process. The proposed method shows a possible 10 % efficiency enhancement at 2.14 GHz in mid-level power regions for the studied LDMOS device under drain bias modulation predicted from a maximum efficiency modulator model. The post-processing method is based on spline interpolation and is useful for the study of any varying envelope signal including digital modulated signals with high peak-to-average ratios.