Carrier pocket engineering applied to “strained” Si/Ge superlattices to design useful thermoelectric materials

The concept of carrier pocket engineering is applied to strained Si/Ge superlattices to obtain a large thermoelectric figure of merit ZT. In this system, the effect of the lattice strain at the Si/Ge interfaces provides another degree of freedom to control the conduction band structure of the superlattice. We explore various geometries and structures to optimize ZT for the whole three-dimensional superlattice. The resultant ZT, calculated for a symmetrized Si(20 A)/Ge(20 A) superlattice grown on a (111) oriented Si0.5Ge0.5 substrate, is 0.96 at 300 K and is shown to increase significantly at elevated temperatures. Such a superlattice can be grown using molecular beam epitaxy.