Interleaved Matched Filtering Method Suitable for ASIC Design

The research of LEO satellite communication system is crucial for the development of modern wireless communication. However, it is significant to realize the design and implementation of the baseband signal processor. In order to adapt to the ASIC design of the multi-mode baseband digital signal processor and optimize the structure of digital receiver, this paper proposes an interleaved digital matched filtering (IDMF) method suitable for ASIC design and bring in the IDMF module which can reduce the consumption of logical resources and power. According to the result of simulation and implementation of FPGA, it is verified that the IDMF method is able to reduce the consumption of logical resources by approximately 15%. Particularly, the multiplier resources decrease close to 1/10 of that in the traditional method.