Charge Trapping Memory Characteristics of Amorphous-Indium–Gallium–Zinc Oxide Thin-Film Transistors With Defect-Engineered Alumina Dielectric

A nonvolatile memory (NVM) based on an amorphous-indium–gallium–zinc oxide (a-IGZO) thin-film transistor (TFT) with defect-engineered gate insulator was demonstrated. The gate insulator was a blocking alumina/storage alumina/tunneling alumina stack structure, which was simply assembled in a single atomic layer deposition step. The memory device showed a positive shift of threshold voltage as large as 14.4 V after +20 V, 1 s programming. In contrast, the memory erasing was not sensitive to negative gate voltage in the dark. Once programmed, the memory can only be light erased. Furthermore, the light combined with a negative bias improved the erasing speed effectively. In addition, a 10-year memory window as large as 7.5 V was extrapolated at room temperature with a charge loss of 34.7%. Based on the observation of blisters in the storage alumina layer after high temperature annealing, Fourier transform infrared spectroscopy measurement and first-principles calculations, the high electron storage capacity can be attributed to the deep defect levels in the storage alumina layer, which were originated from hydrogen impurity. This a-IGZO TFT charge trapping NVM with high performance and simple process is a candidate device for the application of fully functional transparent system on panel.