22µm-pitch 9-bit Column-Parallel Overlapping-Subrange SAR (CPOSSAR) ADC

The Column-Parallel Overlapping-Subrange Successive-Approximation-Register Analog-to-Digital Converter (CPOSSAR ADC) uses a 5-bit split capacitor DAC twice to achieve 9-bit resolution. Its total capacitor area is only 3% of a 9-bit binary weighted DAC and the average switching power is only 12% of a conventional 9-bit DAC. The ADC can perform a 9-bit conversion by first digitizing the 4 most significant bits (MSB) in a coarse conversion stage and then digitizing the 5 least significant bits (LSB) in a fine conversion stage. The accuracy requirement of the DAC is reduced by using overlapping subranges. The proposed ADC achieved an SFDR of 73.6dB and a SINAD of 55dB in post-layout simulation, corresponding to an ENOB of 8.8 bits. The design was fabricated in a TSMC's 0.35µm high-voltage process. The use of overlapping subranges reduced the DNL error from +5.14/-1 LSB to +1.27/-0.92 LSB, and improved the INL error from +5.35/-5.34 LSB to +3.17/-3.18 LSB. At a sampling rate of 1.1MS/s the ADC achieved 41.5dB SFDR, 34.2dB SINAD, and consumed 242µW/channel dynamic power. An individual ADC channel is only 22µm wide. COPSSAR ADCs are a factor of 4, 2, and 2.5 more area efficient than Multiple-ramp Single-slope ADCs, SAR ADCs, and Cyclic ADCs.