Nonlinear Transistor Model Parameter Extraction Techniques: Extrinsic parameter and parasitic elements in III–V HBT and HEMT modeling

Introduction A model formulation that is founded on device physics and optimized for good convergence in different simulator platforms is a first step in providing good, advanced models that will satisfy designers' needs. The degree of extraction complexity will depend directly on the choice of model, but every modeling procedure, regardless of model complexity, relies on accurate device measurements, reliable de-embedding techniques, and methods for parameter extraction. The scope of this chapter is extrinsic parameter extraction. Separating the device parameters from the probe pads' parasitic elements is the first step in the modeling procedure. Thus, the second section will analyze the measurement calibration and parasitic de-embedding techniques that are applicable in III–V HBT and HEMT modeling with an overview of RF test structures for device S -parameter measurements. After the reference planes are moved from the probe pads to the device, the extraction of extrinsic parameters is the next step. The third section will give an overview of extrinsic parameter extraction methods used in HBTs while the fourth section will cover methods used in GaAs-based pHEMTs and GaN-based HEMTs. Extrinsic parameter methods described in Sections 3.3 and 3.4 are mostly applicable for a unit cell device. Large transistor arrays are built up from smaller unit cells that are replicated to achieve a required emitter area (HBT) or gate periphery (pHEMT/HEMT). Accurate modeling of large arrays depends not only on an accurate unit cell model, but also on the choice of the scaling approach and the inclusion of parasitics that are generated by interconnect metals, vias, and bondpads, which modify the impedances of the large array.