Implementation of a 2D low-pass image filtering algorithm on a reconfigurable device.

A device for controlling the phase of an output pulse sequence relative to an input pulse train of the same frequency comprises a multiplier receiving the pulse train from a frequency generator and emitting to a divider a rectangular waveform having a frequency m times that of the pulse train. The divider is controlled by a comparator to divide the frequency of the rectangular waveform by a factor of m DIVIDED 1, m-1, or m, depending on whether the actual phase difference between the pulse train and the sequence is less than, greater than, or equal to a predetermined phase angle, the actual phase difference being communicated to the comparator by a counter registering during each cycle of the pulse train a number of pulses proportional to the phase difference. The divider may energize via a frequency converter a synchronous motor having a rotor connected to a disk whose rate of rotation is monitored by a pickup transmitting a pulse sequence to the counter for phase comparison with the input pulse train, whereby the position of the rotor and the disk upon each rotation may be precisely controlled. The angular position of the rotor and disk may be controlled relative to a second rotor of another synchronous motor, this motor being energized either directly by the frequency generator or indirectly via another multiplier, divider, comparator and counter.