A low power high speed error correction code macro using complementary pass transistor logic circuit

This paper describes the design and implementation of the complementary pass transistor logic (CPL) circuit in a CMOS macro design. The power, speed and noise margin of pass-transistor logic circuits are evaluated and the transistor sizes are optimized for noise margin and circuit performance. This circuit has been successfully implemented in a 64-bit Error Correction Code (ECC) and parity checking macro in the IBM S/390 CMOS processor and significantly improves the power and speed of the ECC macro performance.