Non-complex signal processing in a low-IF receiver for GSM : RF circuits and systems for wireless communications

The low-IF receiver architecture has already proved its effectiveness in mobile radio applications such as GSM. By using an IF of half the channel spacing to facilitate the removal of DC offsets, it achieves the sensitivity of a conventional superhet whilst offering the full integration potential of a direct-conversion receiver. Previous attempts to improve its multi-mode capability have focussed on digitising as much as possible of the IF signal chain with the help of a complex ADC. The channel filtering then moves into the digital domain where reprogramming is comparatively easy for operation in other modes. However, the combination of an increased dynamic range requirement and the need for a complex ADC can make the circuit design problem unduly difficult. In the receiver architecture to be described, the need for a complex ADC is avoided by processing only the real part of the low-IF signal. This substantially simplifies the ADC design whilst retaining all the advantages of a digitised, low-IF receiver. Simplification of the ADC design is the main objective but there is also scope for a 17% reduction in power consumption.