Design of a half-rate receiver for a 10Gbps automotive serial interface with 1-tap-unrolled 4-taps DFE and custom CDR algorithm

Robust and reliable operation of high-speed serial interfaces (HSSI) in automotive environment is challenging. In this paper, we present the analysis and design of a 10Gbps receiver with 4-taps decision feedback equalizer (DFE) with 1-tap unrolled. A novel clock-and-data-recovery (CDR) algorithm is presented to consistently deal with the combined effect of Inter-Symbol Interference (ISI) and DFE on data transitions. The receiver, designed with a 28nm technology, consumes 2.05mW/Gbps and post-layout simulations are reported to show the advantage of the proposed architecture.