Symmetrical ESD trigger and pull-up using BIMOS transistor in advanced CMOS technology

Abstract The purpose of this paper is to present a new trigger design solution to address a double challenge. The first challenge is to trigger a dual back to back SCR during an ESD event with symmetrical response. And the second one is to obtain a pull-up function for the normal mode of the protection. These targets are reached thanks to BIMOS transistor approach compatible with advanced CMOS technology. Moreover, the silicon area constraint is addressed. The study through 3D TCAD simulation is performed on 40 nm and 32 nm and includes Transmission Line Pulse (TLP) measurements of a demonstrator circuit.