A New Single-Rail Energy Recovery Logic with Dual-Rail Outputs

In this paper, a single-rail input energy recovery logic with dual-rail outputs (SRIERL) is proposed. The proposed SRIERL realizes single-rail input operation through the feedback of internal nodes, and it still maintains the characteristic of dual-rail outputs, which makes much easier to work in the cascade. The proposed SRIERL circuits largely simplify the layout designs compared with its ECRL (Efficient Charge Recovery Logic) counterparts. A 1-bit adder and an improved 4-bit carry-lookahead adder are realized based on SRIER. All circuits are verified with HSPICE using a NCSU 45nm technology. The simulation results show that the adders based on SRIERL structure have lower power than those based on ECRL and static CMOS logic.