An Active Impedance-Source Three-Level T-Type Inverter with Reduced Device Count

In this paper, a single-stage active impedance source three-phase T-type inverter is proposed with a reduced component count. Besides the inherent features of the three-level impedancesource inverters -shoot-through (ST) immunity, single-stage power conversion, and continuous input current, the proposed inverter has additional advantages such as increased voltage gain, reduced passive element count, and low voltage stress on devices. Furthermore, the self-balance capacitor voltage capability is the other feature of the proposed inverter. The steady-state analysis, operating principles, and parameter selection guidelines are presented in detail for the proposed inverter. PWM techniques for the proposed inverter including the sinusoidal PWM method and modified space-vector modulation scheme for common-mode voltage reduction are also presented. A comprehensive comparison between the proposed inverter and other three-level impedance-source inverters are shown. The proposed inverter has been validated using the PSIM simulation software and a laboratory prototype is constructed to verify the performance of the proposed inverter.